A complementary metal oxide semiconductor (CMOS) transistor device is a device having both p-channel MOS (PMOS) and n-channel MOS (NMOS) transistors formed on a common semiconductor substrate. A stress liner formed from a material having compressive characteristics can be applied over PMOS devices to improve the mobility of holes in the p-channels. Conversely, a stress liner formed from a material having tensile characteristics can be applied over NMOS devices to improve the mobility of electrons in the n-channels. Some CMOS devices utilize a dual stress liner approach where compressive/tensile stress liners are formed over the PMOS/NMOS devices on the same wafer.
Stress inducing nitride, such as plasma enhanced nitride (PEN) is commonly used to form stress liners, where compressive nitride is applied to PMOS devices and tensile nitride is applied to NMOS devices. Conventional fabrication techniques result in full device coverage of compressive or tensile nitride, and some areas of the wafer may have both in an overlapping arrangement. The different stress liner areas are typically formed using two photolithography-based procedures; one for the tensile nitride areas, and one for the compressive nitride areas. The tensile nitride liner is created by: forming a layer of tensile nitride over the PMOS devices, the NMOS devices, and other devices or elements; forming, exposing, and developing a photoresist mask for the tensile nitride layer (i.e., the tensile nitride mask); and etching away the tensile nitride that remains unprotected by the tensile nitride mask. This results in a tensile liner that covers at least the NMOS devices. After removal of the tensile nitride mask, the compressive liner is created by: forming a layer of compressive nitride over the PMOS and NMOS devices (and over the existing tensile liner); forming, exposing, and developing a photoresist mask for the compressive nitride layer (i.e., the compressive nitride mask); and etching away the compressive nitride that remains unprotected by the compressive nitride mask. This results in a compressive liner that covers the PMOS devices.
For the process described above, the compressive nitride and tensile nitride masks can be automatically generated using suitable design automation tools. Conventional processes (for devices formed on a p-type semiconductor substrate) automatically generate the compressive nitride mask based upon the location of the n-wells of the PMOS devices. In other words, the compressive nitride mask will be automatically designed such that it covers an area that corresponds to the n-wells of the PMOS devices. These conventional processes also automatically generate the tensile nitride mask based upon the location of the n-wells of the PMOS devices—the tensile nitride mask will be automatically designed such that it covers the areas that do not correspond to the n-wells of the PMOS devices. Thus, the areas covered by the tensile nitride mask will include the NMOS devices and all other structures, such as non-transistor structures.
While such automatically generated stress liner masks are easy to define (because they leverage the known dimensions corresponding to the n-wells), they are inherently linked to the layout of the n-wells and, therefore, may not produce stress liner layouts that take full advantage of their compressive/tensile characteristics. For example, in certain situations it might be desirable to fabricate a compressive liner that extends well beyond the boundary of an n-well to enhance the compressive stress imparted by the compressive material. A “customized” compressive nitride mask such as this can be manually designed (drawn), however, such manual design is time consuming and inefficient.